The present invention generally relates to flash memory devices. More particularly, this invention relates to a method and circuitry for the erasing of flash memory cells in order to reduce stress conditions on the tunnel oxide layer of the memory cells and to prevent over-erasing of the memory cells. The erase current is adjusted on a per-cell basis and uses the state of the cell's floating gate to control the erase charge.
As known in the art, flash memory is a type of nonvolatile solid-state memory technology. Flash memory components store information in an array of floating-gate transistors, referred to as cells. NAND flash cells are organized in what are commonly referred to as pages, which in turn are organized in predetermined sections of the component referred to as memory blocks (or sectors). Each cell of a NAND flash memory component has a top or control gate (CG) and a floating gate (FG), the latter being sandwiched between the control gate and the channel of the cell. The floating gate is separated from the control gate by an oxide layer and from the channel by another oxide layer, referred to as the tunnel oxide. Data are stored in a NAND flash cell in the form of a charge on the floating gate which, in turn, defines the channel properties of the NAND flash cell by either augmenting or opposing the charge of the control gate. The process of programming (writing 0's to) a NAND cell requires applying a programming charge to the floating gate by applying a programming voltage to the control gate, which causes the injection of electrons into the floating gate by quantum mechanical tunneling. The process of erasing (writing 1's to) a NAND cell requires removing the programming charge from the floating gate by applying an erase voltage to the device substrate, which pulls electrons from the floating gate. Data are stored, retrieved and erased on a block-by-block basis.
To illustrate, FIG. 1 schematically represents a page of a NAND flash device with memory cells daisy-chained in series. Erasing of the memory cells is accomplished by applying, for example, a 20V erase voltage to a page by closing the bitline select and the ground select transistors (“Bitline Select” and “Ground Select”), thereby forcing the 20V erase voltage on the bitline (“Bitline”) to pass through the control gates (“CG”), which exerts a Fowler-Nordheim field to deplete the floating gate (“FG”) of any program charge.
In single-level cell (SLC) NAND flash devices, the data storage, retrieval and erase technique described above works adequately. However, often an undesired side effect is that the global erase of all cells in one block does not take into account any physical variability between the floating gates of the individual cells, nor does it take into account the different levels of charge of the floating gate in the pre-erase state. Together, the two factors can lead to what is called over-erase or deep depletion of a NAND flash cell's floating gate.
Over-erasing means that, compared to a given baseline level of the floating gate at which the gate transistor returns an “erased” (“closed”) value, the floating gate becomes deep-depleted of electrons. If this happens, a nominal programming charge (electron injection) into the floating gate through the control gate will typically result in a “stuck bit,” that is, a very slow-to-program cell that can result in the cell and, by extension, its entire block being marked as “bad.”
In the case of multi-level cell (MLC) NAND flash, the charge distribution levels are substantially narrower than in the case of SLC NAND flash. In the case of a 2 bit/cell MLC flash device, it is necessary to precisely program four different levels in order to store data. In this case, over-erasing of individual cells can result in catastrophic corruption of data. It is therefore of utmost importance to level the erase state of all cells to the same level. Techniques that have been proposed to achieve this even-leveling effect include decreasing the erase-block size to single word lines or partial blocks, and then applying word line stress or using staggered voltage levels, that is, by applying a pre-erase voltage lower than the target erase voltage. Such a technique is disclosed in U.S. Pat. No. 7,403,427, and is largely directed to solving the problem of over-erasing of single cells. There is an ongoing need for other approaches, for example, to reduce stress on the tunnel oxide layer by preventing exposure to excessive levels of erase voltages.